Switching Converter | PartQuest™ Explore

This design is a detailed circuit implementation of the more abstract "state-average" buck converter model shown in the companion design example: “Buck DC to DC Converter vs. Linear Regulator”. This example includes the low-pass voltage sense circuit, an op-amp implementation of the difference amplifier and the lead-lag compensators, as well as PWM switching control of a power MOSFET. Simulation results for the line and load transients, ripple rejection and the power consumption are very similar to the results from the abstract model.This design uses a number of "datasheet characterized" components, including the power MOSFET (MCH6337), freewheel diode (NRVBA130LT3G) and op-amps (NCV20071), as well as the passive inductor (MSS1583-105KE_) and capacitor (PEG127KA3110Q) of the power stage . The parameter values of these devices were entered directly from the datasheet for the corresponding part, including the "Maximum Ratings" information.While the simulation time for this switching circuit is significantly longer than for the abstract model, more detailed information about the circuit’s signals and components is available. This includes the component stress levels, which are monitored within all the "datasheet" models. For example, the stress indicator for the power inductor shows that the maximum RMS current level is exceeded under this simulated operating condition (i.e. stress_ratio_current_rms &gt; 1.0).The companion design, "TDFS Loop Stability for Buck DC to DC Converter - Switching", demonstrates a method to directly assess the open-loop frequency response, and hence the stability margin, of this converter. The TDFS (Time Domain Frequency Sweep) method circumvents the need for state-average models of the switching elements.

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Managing PWM Waveforms - Buck Converter

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To demonstrate data reduction in a PWM design I've copied and modified Mike Donnelly's Buck DC to DC Converter at https://www.systemvision.com/design/buck-dc-dc-converter-switchingI've added a simplified softstart to simulate startup. Sofstart is implemented by ramping up internal voltages over a 5ms period after a 0.5ms delay for a total startup time of 5.5ms. Mike's load transient is timed to activate after steady state. A line transient can be simulated by adding a pulsed voltage source in series with v_line.The total time to simulate startup, steady state and the load transient is set to 10.5ms of which only the final 4ms involve the response to the transient disturbance. Downloaded .csv files of the output voltage (v_out_buck), inductor current (l1inductor/i), or any other signal cover over 84,000 time points.For a 40us switching cycle, a 1us resolution samples each switching cycle 40 times and requires only 4,000 time points to cover the steady state and load transient response. A voltage source is included in the design to mark off this sampling resolution with a sawtooth signal that starts at 6.5ms. The sawtooth appears at the net named x_smpl. Downloading x_smpl along with v_out_buck to Excel enables edits that reduce the original 84,000 time points to 4,000.To demonstrate the data reduction technique for large .csv downloads,t he design includes a dedicated table voltage source which has been preloaded with a set of 4,000 samples from an earlier simulation. The voltage signal vout_reduced displays those 4,000 samples. The table voltage source can be edited to insert to store reduced data records of any transient response generated by this buck converter.Copies of the table voltage source can be placed into this or any other design in order to display the transient response or apply it to another simulation. This mechanism can be used to test designs that are driven by the buck converter output for their ability to withstand the transient disturbance. Other simulations can be used to compare the simulated response to measured data or to analyze the simulated transient response.Watch for an accompanying blog that will explain how the table voltage source works.

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High-PFC 1.8KW AC/DC Flyback Converter - Mike D.

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Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

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High-PFC 1.8KW AC/DC Flyback Converter

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High-PFC 1.8KW AC/DC Flyback Converter

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TDFS Input Impedance of Step-Down (Buck) DC to DC Converter - Switching

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Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

Description

This example demonstrates the use of the TDFS method (Time Domain Frequency Sweep) to measure the input impedance of a switching DC/DC power converter. The converter circuit is identical to the design shown in the companion example: “Step-Down (Buck) DC to DC Converter - Switching”.In this example, the TDFS impedance measurement model applies a 12V DC bias to the line input, in addition to a sinusoidal stimulus with 3V peak amplitude, and a frequency range from 3 kHz to 30 kHz. The input current is measured and the impedance vs. frequency is computed. The results show that the impedance magnitude (blue waveform) is approximately 5.0 Ohms at low frequency, This is approximately the reflected value of the 1 Ohm load resistor, multiplied by the effective DC/DC conversion ratio squared: 1 Ohm * (12.0/5.0)**2 = 5.76 OhmThe phase measurement (red waveform) shows -175 degrees at low frequency, indicating that this is effectively a "negative resistance". That is, the input current decreases when the line voltage increases. This behavior can be observed directly in the time domain waveforms, where the line voltage (brown waveform) and the input current (green waveform) are almost completely out of phase at 3 kHz. This negative impedance, or constant power load characteristic, can be destabilizing in power distribution systems. This will be demonstrated in a related design, and in Part 3 of the TDFS Blog Series, coming soon!

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TDFS Loop Stability for Step-Down DC to DC (Buck) Converter - Switching

Designer19

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11 years 10 months

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Member of the PartQuest Explore Development Team. Focused on modeling and simulation of analog, mixed-signal and multi-discipline systems covering a broad range of applications, including power electronics, controls and mechatronic systems.

Description

This example demonstrates the TDFS (Time Domain Frequency Sweep) Loop Stability Instrument Model. It is used to compute the open-loop transfer function of an operating (closed-loop) switching power converter. There is no need for state-average or continuous equivalent models for the modulator section of the design, as normally needed for frequency-domain (or "AC") analysis. Rather, the actual circuit component models can be used directly, because the open-loop transfer function is computed from time-domain simulation results.In this case, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor. The TDFS measurement instrument indicates that the open-loop gain crossover frequency is at 26 kHz, and the phase margin is just under 60 degrees. This verifies that the opamp-based lead-lag compensator is providing adequate stability margin under these operating conditions.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.The companion example, "Step-Down (Buck) DC to DC Converter - Switching", shows the line and load transient response of this converter design. Another companion example, "Step-Down (Buck) DC to DC Converter - Continuous", uses a state-average model of the switching (or modulator) section of the converter, so it supports traditional "AC" or frequency-domain analysis.

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Buck DC to DC Converter - Switching

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This design is a detailed circuit implementation of the more abstract "state-average" buck converter model shown in the companion design example: “Buck DC to DC Converter vs. Linear Regulator”. This example includes the low-pass voltage sense circuit, an op-amp implementation of the difference amplifier and the lead-lag compensators, as well as PWM switching control of a power MOSFET. Simulation results for the line and load transients, ripple rejection and the power consumption are very similar to the results from the abstract model.This design uses a number of "datasheet characterized" components, including the power MOSFET (MCH6337), freewheel diode (NRVBA130LT3G) and op-amps (NCV20071), as well as the passive inductor (MSS1583-105KE_) and capacitor (PEG127KA3110Q) of the power stage . The parameter values of these devices were entered directly from the datasheet for the corresponding part, including the "Maximum Ratings" information.While the simulation time for this switching circuit is significantly longer than for the abstract model, more detailed information about the circuit’s signals and components is available. This includes the component stress levels, which are monitored within all the "datasheet" models. For example, the stress indicator for the power inductor shows that the maximum RMS current level is exceeded under this simulated operating condition (i.e. stress_ratio_current_rms &gt; 1.0).The companion design, "TDFS Loop Stability for Buck DC to DC Converter - Switching", demonstrates a method to directly assess the open-loop frequency response, and hence the stability margin, of this converter. The TDFS (Time Domain Frequency Sweep) method circumvents the need for state-average models of the switching elements.

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Buck DC to DC Converter - Switching

Designer21

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11 years 10 months

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Member of the PartQuest Explore team.

Description

This design is a detailed circuit implementation of the more abstract "state-average" buck converter model shown in the companion design example: “Buck DC to DC Converter vs. Linear Regulator”. This example includes the low-pass voltage sense circuit, an op-amp implementation of the difference amplifier and the lead-lag compensators, as well as PWM switching control of a power MOSFET. Simulation results for the line and load transients, ripple rejection and the power consumption are very similar to the results from the abstract model.This design uses a number of "datasheet characterized" components, including the power MOSFET (MCH6337), freewheel diode (NRVBA130LT3G) and op-amps (NCV20071), as well as the passive inductor (MSS1583-105KE_) and capacitor (PEG127KA3110Q) of the power stage . The parameter values of these devices were entered directly from the datasheet for the corresponding part, including the "Maximum Ratings" information.While the simulation time for this switching circuit is significantly longer than for the abstract model, more detailed information about the circuit’s signals and components is available. This includes the component stress levels, which are monitored within all the "datasheet" models. For example, the stress indicator for the power inductor shows that the maximum RMS current level is exceeded under this simulated operating condition (i.e. stress_ratio_current_rms &gt; 1.0).The companion design, "TDFS Loop Stability for Buck DC to DC Converter - Switching", demonstrates a method to directly assess the open-loop frequency response, and hence the stability margin, of this converter. The TDFS (Time Domain Frequency Sweep) method circumvents the need for state-average models of the switching elements.

About text formats

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