D Flip-Flop experiment https://explore.partquest.com/node/414 <iframe allowfullscreen="true" referrerpolicy="origin-when-cross-origin" frameborder="0" width="100%" height="720" scrolling="no" src="https://explore.partquest.com/node/414"></iframe> Title Description <p>This is an experiment to explore the D Flip-Flop (or D Latch). </p><p>The single element DFF, on the left side of the diagram, is a single VHDL model implementation of a DFF. </p><p>The logic circuit to the right is a gate-level version of the same function. </p><p>The test inputs are digital signals: data, clk, set, and reset. These are pulsed in various sequences to explore all of the combinations needed to exercise all of the states of a DFF.</p><p>The same input signals are fed into the gate-level version of a DFF (hover over the input signals to see the corresponding signal, of the same name, highlighted on the other circuit).</p><p>The corresponding outputs, dff_q and gates_q, fundamentally match. The exception is the output when both set and reset are high. For the DFF model, this is undefined and produces an 'X' state. Where for the gates, the output is defined.</p> About text formats Tags DFFD Flip-FlopD LatchSet-Reset Select a tag from the list or create your own.Drag to re-order taxonomy terms. License - None -
