PartQuest Explore Promote

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

NCV6356_Demo_Board_fastsim

Bob Davis
Designer40261

Member for

8 years 7 months

76

designs

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

Hierarchical NCV6356 Demo Board buck converter.Ideal switches replace MOSFETs to maximize simulation speed. Best usage is to verify desired behavior over millisecond to tens of ms. Best used to monitor behaviors covering hundreds or more switching cycles.-------------------------------------------------------------------------------------Some useful waveforms can be displayed by probing the chip module. * Expand Fsw_cal and select tbase_rd_out to display Fsw regulation. tbase_rd_out seeks and maintains a constant level of 80 units by setting a controlling value in the Kton waveform. * Select state_of_chip to trace power-up sequence and ishort * Expand Ipk_detect and select N_violations to monitor progress towards ishort detection. * Overlay plots of FBint and Vintl to display voltage resolution,-------------------------------------------------------------------------------------See NCV6356_Demo_Board for an identical design using MOSFET switches to accurately account for power dissipation.-------------------------------------------------------------------------------------See wrap_NCV6356_combined for a schematic representation of the chip model. MOSFET and ideal switch versions are derived from a common netlist generated from this design with portions commented out.Version6_NCV6356_and_DemoBoard combines the above chip model with external buck converter circuitry to produce a single level flattened hierarchy usable to develop and test the chip model.

wrap_NCV6356_fastsim

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

groups

wrap_NCV6356_MOSFET

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

groups

NCV6356_Demo_Board_fastsim

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

groups

Description

Hierarchical NCV6356 Demo Board buck converter.Ideal switches replace MOSFETs to maximize simulation speed. Best usage is to verify desired behavior over millisecond to tens of ms. Best used to monitor behaviors covering hundreds or more switching cycles.-------------------------------------------------------------------------------------Some useful waveforms can be displayed by probing the chip module. * Expand Fsw_cal and select tbase_rd_out to display Fsw regulation. tbase_rd_out seeks and maintains a constant level of 80 units by setting a controlling value in the Kton waveform. * Select state_of_chip to trace power-up sequence and ishort * Expand Ipk_detect and select N_violations to monitor progress towards ishort detection. * Overlay plots of FBint and Vintl to display voltage resolution,-------------------------------------------------------------------------------------See NCV6356_Demo_Board for an identical design using MOSFET switches to accurately account for power dissipation.-------------------------------------------------------------------------------------See wrap_NCV6356_combined for a schematic representation of the chip model. MOSFET and ideal switch versions are derived from a common netlist generated from this design with portions commented out.Version6_NCV6356_and_DemoBoard combines the above chip model with external buck converter circuitry to produce a single level flattened hierarchy usable to develop and test the chip model.

wrap_NCV6356_combined

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

groups

on_bb_NCV6356_I2C_xmit

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

groups

Version6fast_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

Member for

7 years 2 months

10

designs

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

Identical to Version 6 except FETs and drivers are completely removed------------------------------------------------------------------------------------Version 6 of the NCV6356 model and demo-board is a first step towards wrapping the model. Revisions include: 1. A chip-level mock up to facilitate and document the manual edits needed to wrap the model into a single hierarchical module. 1a. NCV6356 Generics 1b. NCV6356 datasheet specs and other global constants 1c. Comments for each global constant index the submodule(s) that reference the constant 1d Schematic symbol 2. FID removed from the external GUI, added to Ipeak detector and to chip-level mock up. FID reformatted as integer type compatible with SV property dialog. 3. fast_sim generic added to chip-level mock-up select MOSFET vs. ideal switches. 4. The control input to Mike's variable load current model is changed from "real" to "current" so that SV will plot the load current and control on the same axis. 5. BB module ground connections correctly sorted between Agnd and Pgnd. 6. Wires connected to NCV6356 pins are relabeled using Mike's standard p<pin>_<netname>.</netname></pin>E.g., P2_Vout identifies Vout on pin 2. 6a Wires added to access NCV6356 pins from left or right side of the schematic. 6b Short (i.e., short_circuit) connectors split wires for connection to two or three pins. See, for example, SW, Pvin. 7. As proposed by Mike Donnelly, the coder side of the I2C interface is restored to a GUI driving bits2integer and integers2vector modules to expose the organization of the integer-vector for future reference, 8. The controller module outputs the state of the model for easier access in probing or waveform analyzer display.--------------------------------------------------------------------------------------Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

Version5_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

Member for

7 years 2 months

10

designs

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

Version6_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

Member for

7 years 2 months

10

designs

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

Version 6 of the NCV6356 model and demo-board is a first step towards wrapping the model. Revisions include: 1. A chip-level mock up to facilitate and document the manual edits needed to wrap the model into a single hierarchical module. 1a. NCV6356 Generics 1b. NCV6356 datasheet specs and other global constants 1c. Comments for each global constant index the submodule(s) that reference the constant 1d Schematic symbol 2. FID removed from the external GUI, added to Ipeak detector and to chip-level mock up. FID reformatted as integer type compatible with SV property dialog. 3. fast_sim generic added to chip-level mock-up select MOSFET vs. ideal switches. 4. The control input to Mike's variable load current model is changed from "real" to "current" so that SV will plot the load current and control on the same axis. 5. BB module ground connections correctly sorted between Agnd and Pgnd. 6. Wires connected to NCV6356 pins are relabeled using Mike's standard p<pin>_<netname>.</netname></pin>E.g., P2_Vout identifies Vout on pin 2. 6a Wires added to access NCV6356 pins from left or right side of the schematic. 6b Short (i.e., short_circuit) connectors split wires for connection to two or three pins. See, for example, SW, Pvin. 7. As proposed by Mike Donnelly, the coder side of the I2C interface is restored to a GUI driving bits2integer and integers2vector modules to expose the organization of the integer-vector for future reference, 8. The controller module outputs the state of the model for easier access in probing or waveform analyzer display.--------------------------------------------------------------------------------------Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.