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This example demonstrates the TDFS (Time Domain Frequency Sweep) Loop Stability Instrument Model. It is used to compute the open-loop transfer function of an operating (closed-loop) switching power converter. There is no need for state-average or continuous equivalent models for the modulator section of the design, as normally needed for frequency-domain (or "AC") analysis. Rather, the actual circuit component models can be used directly, because the open-loop transfer function is computed from time-domain simulation results.In this case, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor. The TDFS measurement instrument indicates that the open-loop gain crossover frequency is at 26 kHz, and the phase margin is just under 60 degrees. This verifies that the opamp-based lead-lag compensator is providing adequate stability margin under these operating conditions.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.The companion example, "Step-Down (Buck) DC to DC Converter - Switching", shows the line and load transient response of this converter design. Another companion example, "Step-Down (Buck) DC to DC Converter - Continuous", uses a state-average model of the switching (or modulator) section of the converter, so it supports traditional "AC" or frequency-domain analysis.

Ripple Free Buck

Norm
Designer43361

Norm

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8 years 7 months

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This design starts from a copy of Mike Donnelly's "TDFS Loop Stability for Step-Down DC to DC (Buck) Converter - Switching". I've inserted a moving average filter between the output capacitor bank and the output to the load. With the averaging window with set equal to the 5us switching period, the steady state switching ripple is completely cancelled. The price is a 2.5us delay imposed by the filter's linear phase response.As with Mike's example, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor.The TDFS measurement instrument generates a Bode plot for the open-loop transfer function that compares the gain crossover and phase margin to the original values of 60 degrees PM @ a 26 KHz gain crossover.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.

ANKIT
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ANKIT

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5 years 11 months

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NCV891930MW00 Virtual Demo Board

RobertDavis
Designer256

RobertDavis

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9 years 6 months

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This version of the NCV891930MW00 "Virtual Evaluation Board" represents most of the features of the 3.3 V/5.0 V output part. By changing various input stimulus and loading conditions, you can test these capabilities in the context of their intended usage.For the nominal configuration, the input voltage is set to 12V, the synci source is delayed for 10 msec (well beyond the simulation end-time), and the load resistance is fixed at 1 Ohm until 500 us, then it jumps to 10 kOhm for 100 us, then back to 1 Ohm. The soft-start operates normally, but during the high resistance operation of the load transient, a single pulse-skip interval is observed. You can zoom in on the PWM signal and see that only two 500 kHz pulses were applied during the “burst” interval, but it will generate 3 pulses under other operating conditions. You can also see that the PWM frequency is spread-spectrum after the soft-start is complete, by measuring the clock frequency (as a waveform) in the main waveform viewer.To test the “GH continuous ON” behavior, you can select the “DC” option in the load resistance function generator to set the value to a fixed 1 Ohm, and set the input voltage to 5.5V. In the simulation you'll observe several long periods of "continuous GH" operation, with 200 ns boost recharge windows every 16 us, after soft-start has finished.To test SYNCI operation, set the input voltage to 12V and the load resistance to “Pulse” (i.e. back to their original values), and then change the synci source delay to 10 ns (instead of 10 ms). Then the device will operate in forced PWM mode, with negative inductor currents allowed during the high load resistance period (i.e. not diode-emulation), and no pulse-skip. Other features can also be tested (high voltage frequency fold-back, output voltage select, LDO bypass jumper removed, etc.). In addition, you can force abnormal operating states using the two fixed logic sources available in the lower left corner of the schematic. For example, if the controller signal “d_spread_spectrum” is disconnected right at the input to the oscillator, and then a new net is connected from “d_set0” to that open input port, then the oscillator's spread-spectrum function will be disabled regardless of the normal controller commanded behavior.Notes: (1) Because a simplified version of the resistor divider network and compensation is used, the model will regulate above the target output voltage at light loads. The the real IC will regulate within specifications. (2) In order to reduce the simulation time, the softstart capacitor value has been adjusted to reduce the softstart time. The value used in this project does not reflect the suggested value from the evaluation board schematic. The desired capacitor value should be selected based on the equation provided in the datasheet.

NCV891930MW01 Virtual Demo Board

RobertDavis
Designer256

RobertDavis

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9 years 6 months

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This version of the NCV891930MW01 "Virtual Evaluation Board" represents most of the features of the 3.65 V/4.0V output part. By changing various input stimulus and loading conditions, you can test these capabilities in the context of their intended usage.For the nominal configuration, the input voltage is set to 12V, the synci source is delayed for 10 msec (well beyond the simulation end-time), and the load resistance is fixed at 1 Ohm until 500 us, then it jumps to 10 kOhm for 100 us, then back to 1 Ohm. The soft-start operates normally, but during the high resistance operation of the load transient, a single pulse-skip interval is observed. You can zoom in on the PWM signal and see that only two 500 kHz pulses were applied during the “burst” interval, but it will generate 3 pulses under other operating conditions. You can also see that the PWM frequency is spread-spectrum after the soft-start is complete, by measuring the clock frequency (as a waveform) in the main waveform viewer.To test the “GH continuous ON” behavior, you can select the “DC” option in the load resistance function generator to set the value to a fixed 1 Ohm, and set the input voltage to 5.5V. In the simulation you'll observe several long periods of "continuous GH" operation, with 200 ns boost recharge windows every 16 us, after soft-start has finished.To test SYNCI operation, set the input voltage to 12V and the load resistance to “Pulse” (i.e. back to their original values), and then change the synci source delay to 10 ns (instead of 10 ms). Then the device will operate in forced PWM mode, with negative inductor currents allowed during the high load resistance period (i.e. not diode-emulation), and no pulse-skip. Other features can also be tested (high voltage frequency fold-back, output voltage select, LDO bypass jumper removed, etc.). In addition, you can force abnormal operating states using the two fixed logic sources available in the lower left corner of the schematic. For example, if the controller signal “d_spread_spectrum” is disconnected right at the input to the oscillator, and then a new net is connected from “d_set0” to that open input port, then the oscillator's spread-spectrum function will be disabled regardless of the normal controller commanded behavior.Notes: (1) Because a simplified version of the resistor divider network and compensation is used, the model will regulate above the target output voltage at light loads. The the real IC will regulate within specifications. (2) In order to reduce the simulation time, the softstart capacitor value has been adjusted to reduce the softstart time. The value used in this project does not reflect the suggested value from the evaluation board schematic. The desired capacitor value should be selected based on the equation provided in the datasheet.

NCV881930 Virtual Demo Board

RobertDavis
Designer256

RobertDavis

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9 years 6 months

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SMSSA Theory - Test rev 2 Baseline

Norm
Designer43361

Norm

Member for

8 years 7 months

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Description

This example demonstrates the TDFS (Time Domain Frequency Sweep) Loop Stability Instrument Model. It is used to compute the open-loop transfer function of an operating (closed-loop) switching power converter. There is no need for state-average or continuous equivalent models for the modulator section of the design, as normally needed for frequency-domain (or "AC") analysis. Rather, the actual circuit component models can be used directly, because the open-loop transfer function is computed from time-domain simulation results.In this case, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor. The TDFS measurement instrument indicates that the open-loop gain crossover frequency is at 26 kHz, and the phase margin is just under 60 degrees. This verifies that the opamp-based lead-lag compensator is providing adequate stability margin under these operating conditions.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.The companion example, "Step-Down (Buck) DC to DC Converter - Switching", shows the line and load transient response of this converter design. Another companion example, "Step-Down (Buck) DC to DC Converter - Continuous", uses a state-average model of the switching (or modulator) section of the converter, so it supports traditional "AC" or frequency-domain analysis.

SMSSA Theory - Test rev 2

Norm
Designer43361

Norm

Member for

8 years 7 months

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Description

This example demonstrates the TDFS (Time Domain Frequency Sweep) Loop Stability Instrument Model. It is used to compute the open-loop transfer function of an operating (closed-loop) switching power converter. There is no need for state-average or continuous equivalent models for the modulator section of the design, as normally needed for frequency-domain (or "AC") analysis. Rather, the actual circuit component models can be used directly, because the open-loop transfer function is computed from time-domain simulation results.In this case, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor. The TDFS measurement instrument indicates that the open-loop gain crossover frequency is at 26 kHz, and the phase margin is just under 60 degrees. This verifies that the opamp-based lead-lag compensator is providing adequate stability margin under these operating conditions.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.The companion example, "Step-Down (Buck) DC to DC Converter - Switching", shows the line and load transient response of this converter design. Another companion example, "Step-Down (Buck) DC to DC Converter - Continuous", uses a state-average model of the switching (or modulator) section of the converter, so it supports traditional "AC" or frequency-domain analysis.

SMSSA Theory Test

Norm
Designer43361

Norm

Member for

8 years 7 months

designs

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Description

This example demonstrates the TDFS (Time Domain Frequency Sweep) Loop Stability Instrument Model. It is used to compute the open-loop transfer function of an operating (closed-loop) switching power converter. There is no need for state-average or continuous equivalent models for the modulator section of the design, as normally needed for frequency-domain (or "AC") analysis. Rather, the actual circuit component models can be used directly, because the open-loop transfer function is computed from time-domain simulation results.In this case, the converter is operating at 200kHz switching frequency, and is converting the 12V DC input to a regulated 5V output, while supplying a 5A current to the 1 Ohm load resistor. The TDFS measurement instrument indicates that the open-loop gain crossover frequency is at 26 kHz, and the phase margin is just under 60 degrees. This verifies that the opamp-based lead-lag compensator is providing adequate stability margin under these operating conditions.Note that the TDFS instrument model characterizes the open loop transfer function by injecting a small sinusoidal stimulus signal in series with the loop, and then measures the complex ratio of the return signal to the injected signal, is described in:D. Venable, “Testing Power Sources for Stability”, Venable technical paper #1, Venable Industries.The companion example, "Step-Down (Buck) DC to DC Converter - Switching", shows the line and load transient response of this converter design. Another companion example, "Step-Down (Buck) DC to DC Converter - Continuous", uses a state-average model of the switching (or modulator) section of the converter, so it supports traditional "AC" or frequency-domain analysis.

Buck DC to DC Converter - save and regenerate waveforms

UCM
Designer207769

UCM

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5 years 11 months

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This design is a copy of Mike Donnelly's Buck DC to DC Converter modified to demonstrate data reduction for downloaded waveforms. For more information about the buck converter you can find Mike's design athttps://www.systemvision.com/design/buck-dc-dc-converter-switchingThis design ramps up internal voltages for a simplified model of softstart. Mike's load transient is timed to activate after steady state. The L1 current rises after an initial spike. This current charges the output cap to generate a rising output voltage. That output voltage rises past the 5V setpoint until steady state sets in around 5.5V. After that Vout settles back to its steady state level. The load transient triggers disturbances in Vout at both edges of the transient.For further analysis of steady state and line/load transients, an x-sampling voltage source is added to reduce the size of the .csv data and to skip over startup. Data reduced files are generated in an Excel post-processing session based on the x-sampling voltage peaks.The reduced data can be read back into SystemVision or other appllications to display the waveforms,compare them to waveforms from another source or use them as sources in further simulations.