Design example from the Webinar: “Creating New Components, Part 2: “Making VHDL-AMS Models”. View the archive presentation here:

http://www.systemvision.com/webinars

This 555 Timer application circuit is configured as an astable multivibrator with a frequency-modulated output. The two 10kOhm resistors and the 1uF capacitor on the left set the output duty cycle and the base oscillation frequency. The controlled variable resistor on the right (attached to the CTRL pin of the 555 Timer) adjusts that frequency by compressing the state transition threshold voltage levels on the TRIG and THR pins (see plot on the left).

The mixed-signal 555 Timer model was created using the IEEE Standard VHDL-AMS modeling language. You can right-click on the symbol and choose "View/Copy Model" to see the digital logic and analog equations that represent the main characteristics of the 555 Timer.

A companion design example, "Graphical Model Of 555 Timer" shows the equivalent application circuit, but the 555 Timer model itself is "assembled" from building-block models from the systemvision.com library, rather than a directly using VHDL-AMS.

Design example from the Webinar: “Creating New Components, Part 2: “Making VHDL-AMS Models”. View the archive presentation here:

http://www.systemvision.com/webinars