Electro-Thermal Design Part 1: Digital Electronics

by Mike Donnelly
2 September 2020

Electro-Thermal Design Part 1: Digital Electronics

A new thermal model generation capability has recently been provided in Simcenter Flotherm. It will not only improve the accuracy and efficacy of the electro-thermal design process, but will also be easy for electronic circuit designers to use. In this article, which is Part 1 of a series, I’ll focus on an example application: A “smartphone”. This is intended to represent systems that are primarily composed of digital electronics devices.

The electro-thermal dynamics of a smartphone are shown in the “Live” (interactive) schematic shown below. Most of the components represent digital ICs that perform key functions in the phone, but only their electrical power consumption and heat transfer to the board/enclosure is modeled. The power input at each “operating state” (idle, streaming and gaming) is specified by the user, along with the corresponding calibration voltage and clock rate. The actual power consumed and heat dissipated by the device will vary as those operating parameters are changed during a simulation run. For example, higher power dissipation will occur at higher clock rates.

The "analog" components, which include the battery and a state-average model of a buck power converter, also contribute heat corresponding to the actual (time-varying) load current.

The "thermals" of the board/enclosure are represented by an IEEE Standard VHDL-AMS "Thermal Netlist" model, shown on the far right of the schematic. This model was generated by Simcenter Flotherm for a specific board layout, based on a detailed 3D-CFD analysis. The generated model was directly and easily imported into this electro-thermal schematic, so that it could be simulated in this operational system context. To learn more about generating thermal netlists from the 3D thermal analysis perspective, please see this blog on Simcenter Flotherm 2020.1 by Byron Blackmore.

This type of design can be used during the development process of a "maximum clock-rate tracking algorithm", shown on the far left of the schematic. The sampled-data algorithm is attempting to keep the temperature above the processor, as measured by a thermistor at that sense location, between two limits. It does this by adjusting the global clock rate that is distributed to all the digital components. The reader can change the parameters of the algorithm and run new simulations to see their effect. For example, you can set different temperature limits, sample rates, or the minimum and maximum clock-rates. You can also test various operating conditions, such as higher or lower battery voltage or internal resistance (i.e. to simulate different states-of-charge), as well as the calibrated power dissipation levels of the CPU and GPU.

Just for Fun!

Try changing the temperature sample_period on the control algorithm from 10 to 20 seconds. Note that the clock rate no longer drops to 2GHz  while "gaming". This is because the extra sampling delay gives the temperature transient more time to fall below the upper limit, after the initial clock-rate is decreased from 8 to 4 GHz. Next try sample_period = 5 seconds, and notice that the performance is even worse; the clock rate spends almost half the time at 2 GHz while gaming!