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Identical to Version 6 except FETs and drivers are completely removed------------------------------------------------------------------------------------Version 6 of the NCV6356 model and demo-board is a first step towards wrapping the model. Revisions include: 1. A chip-level mock up to facilitate and document the manual edits needed to wrap the model into a single hierarchical module. 1a. NCV6356 Generics 1b. NCV6356 datasheet specs and other global constants 1c. Comments for each global constant index the submodule(s) that reference the constant 1d Schematic symbol 2. FID removed from the external GUI, added to Ipeak detector and to chip-level mock up. FID reformatted as integer type compatible with SV property dialog. 3. fast_sim generic added to chip-level mock-up select MOSFET vs. ideal switches. 4. The control input to Mike's variable load current model is changed from "real" to "current" so that SV will plot the load current and control on the same axis. 5. BB module ground connections correctly sorted between Agnd and Pgnd. 6. Wires connected to NCV6356 pins are relabeled using Mike's standard p<pin>_<netname>.</netname></pin>E.g., P2_Vout identifies Vout on pin 2. 6a Wires added to access NCV6356 pins from left or right side of the schematic. 6b Short (i.e., short_circuit) connectors split wires for connection to two or three pins. See, for example, SW, Pvin. 7. As proposed by Mike Donnelly, the coder side of the I2C interface is restored to a GUI driving bits2integer and integers2vector modules to expose the organization of the integer-vector for future reference, 8. The controller module outputs the state of the model for easier access in probing or waveform analyzer display.--------------------------------------------------------------------------------------Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

Version5_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

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7 years 2 months

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Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

Version6_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

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7 years 2 months

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Version 6 of the NCV6356 model and demo-board is a first step towards wrapping the model. Revisions include: 1. A chip-level mock up to facilitate and document the manual edits needed to wrap the model into a single hierarchical module. 1a. NCV6356 Generics 1b. NCV6356 datasheet specs and other global constants 1c. Comments for each global constant index the submodule(s) that reference the constant 1d Schematic symbol 2. FID removed from the external GUI, added to Ipeak detector and to chip-level mock up. FID reformatted as integer type compatible with SV property dialog. 3. fast_sim generic added to chip-level mock-up select MOSFET vs. ideal switches. 4. The control input to Mike's variable load current model is changed from "real" to "current" so that SV will plot the load current and control on the same axis. 5. BB module ground connections correctly sorted between Agnd and Pgnd. 6. Wires connected to NCV6356 pins are relabeled using Mike's standard p<pin>_<netname>.</netname></pin>E.g., P2_Vout identifies Vout on pin 2. 6a Wires added to access NCV6356 pins from left or right side of the schematic. 6b Short (i.e., short_circuit) connectors split wires for connection to two or three pins. See, for example, SW, Pvin. 7. As proposed by Mike Donnelly, the coder side of the I2C interface is restored to a GUI driving bits2integer and integers2vector modules to expose the organization of the integer-vector for future reference, 8. The controller module outputs the state of the model for easier access in probing or waveform analyzer display.--------------------------------------------------------------------------------------Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

NCV6356_(Norm_V5)

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

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7 years 2 months

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Description

Version 5 of the NCV6356 model and demo-board includes the following revisions to the preliminary version. 1. I2C defaults (See ON_BB_NCV6356_I2C_GUI) are taken from the preliminary datasheet as excerpted by Phil Debosque. 2. Tftr delays (See ON_BB_NCV6356_I2C_GUI) are taken from the high end of the debounce ranges as listed in the preliminary datasheet 3. Unused generics are deleted from the GUI model. 4. EN and VSEL are regenerated as analog pins with 1-digital A/D 5. DVSrate is expressed using "ndnnn mV" notation. and 6. Quiescent currents are modeled using JMD's variable load current model driven from the NCV6356 controller.--------------------------------------------------------------------------------------Version 5 adapts Mike Donnelly's approach to pass I2C values to the chip through an integer-vector bus with external signal generation wrapped into a hierarchical module. The top level of that hierarchy presents a GUI to the user that is derived from the official ON Semi GUI for the NCV6356 Demo Board.The SystemVision GUI module experiments with generic names based on the labeling of the ON Semi GUI. For cosmetic purposes the SV GUI introduces generics whose sole use is to partition the SV GUI into regions seen on the ON Semi GUI. These innovations should be scrutinized to make sure that they simplify the GUI rather than to clutter it.Models (Subject to review): * IPEAK/ISHORT hazard detection, correction and recovery. * Power Good. * Preliminary version of DC quiescent currents excluding delay phases in power up.Work remaining includes completion of the Iq currents and estimation of power dissipation.---------------------------------------------------------------------------------------Note: I have kept the option to select MOSFET or ideal switches. the final wrapped model will either offer only the MOSFET option or will be accompanied by a "fast" design using only the switches.

ePower_140

ebookaktiv
Designer152721

ebookaktiv

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7 years 1 month

109

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ePower_100

ebookaktiv
Designer152721

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7 years 1 month

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V4B_NCV6356_DemoBoard_Testbench_Phil

PhilDEBOSQUE
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PhilDEBOSQUE

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V 4_NCV6356_DemoBoard

PhilDEBOSQUE
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PhilDEBOSQUE

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NormscopyofMikesNCV891930_EvalBd_fast_v8

Norm
Designer43361

Norm

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8 years 7 months

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Fast (Ideal Switches) Version 8 of NCV891930 Virtual Eval Board

Norm
Designer43361

Norm

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8 years 7 months

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Description

This version of the NCV891930 "Virtual Evaluation Board" simulates &gt; 4x faster than if full MOSFET switch models are used. This model represents most of the features of the part. By changing various input stimulus and loading conditions, you can test these capabilities in the context of their intended usage.For the nominal configuration, the input voltage is set to 12V, the synci source is delayed for 10 msec (well beyond the simulation end-time), and the load resistance is fixed at 1 Ohm until 500 us, then it jumps to 10 kOhm for 100 us, then back to 1 Ohm. The soft-start operates normally, but during the high resistance operation of the load transient, a single pulse-skip interval is observed. You can zoom in on the PWM signal and see that only two 500 kHz pulses were applied during the “burst” interval, but it will generate 3 pulses under other operating conditions. You can also see that the PWM frequency is spread-spectrum after the soft-start is complete, by measuring the clock frequency (as a waveform) in the main waveform viewer.To test the “GH continuous ON” behavior, you can select the “DC” option in the load resistance function generator to set the value to a fixed 1 Ohm, and set the input voltage to 5.2V. In the simulation you'll observe several long periods of "continuous GH" operation, with 200 ns boost recharge windows every 16 us, after soft-start has finished.To test SYNCI operation, set the input voltage to 12V and the load resistance to “Pulse” (i.e. back to their original values), and then change the synci source delay to 10 ns (instead of 10 ms). Then the device will operate in forced PWM mode, with negative inductor currents allowed during the high load resistance period (i.e. not diode-emulation), and no pulse-skip. Other features can also be tested (high voltage frequency fold-back, output voltage select, LDO bypass jumper removed, etc.). In addition, you can force abnormal operating states using the two fixed logic sources available in the lower left corner of the schematic. For example, if the controller signal “d_spread_spectrum” is disconnected right at the input to the oscillator, and then a new net is connected from “d_set0” to that open input port, then the oscillator's spread-spectrum function will be disabled regardless of the normal controller commanded behavior.