Buck Converter | PartQuest™ Explore

Application Area

Dagi
Designer190236

Dagi

Member for

6 years 8 months

1

designs

1

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

To demonstrate data reduction in a PWM design I've copied and modified Mike Donnelly's Buck DC to DC Converter at https://www.systemvision.com/design/buck-dc-dc-converter-switchingI've added a simplified softstart to simulate startup. Sofstart is implemented by ramping up internal voltages over a 5ms period after a 0.5ms delay for a total startup time of 5.5ms. Mike's load transient is timed to activate after steady state. A line transient can be simulated by adding a pulsed voltage source in series with v_line.The total time to simulate startup, steady state and the load transient is set to 10.5ms of which only the final 4ms involve the response to the transient disturbance. Downloaded .csv files of the output voltage (v_out_buck), inductor current (l1inductor/i), or any other signal cover over 84,000 time points.For a 40us switching cycle, a 1us resolution samples each switching cycle 40 times and requires only 4,000 time points to cover the steady state and load transient response. A voltage source is included in the design to mark off this sampling resolution with a sawtooth signal that starts at 6.5ms. The sawtooth appears at the net named x_smpl. Downloading x_smpl along with v_out_buck to Excel enables edits that reduce the original 84,000 time points to 4,000.To demonstrate the data reduction technique for large .csv downloads,t he design includes a dedicated table voltage source which has been preloaded with a set of 4,000 samples from an earlier simulation. The voltage signal vout_reduced displays those 4,000 samples. The table voltage source can be edited to insert to store reduced data records of any transient response generated by this buck converter.Copies of the table voltage source can be placed into this or any other design in order to display the transient response or apply it to another simulation. This mechanism can be used to test designs that are driven by the buck converter output for their ability to withstand the transient disturbance. Other simulations can be used to compare the simulated response to measured data or to analyze the simulated transient response.Watch for an accompanying blog that will explain how the table voltage source works.

About text formats

NCV6356_Demo_Board_fastsim_Phil

PhilDEBOSQUE
Designer146986

PhilDEBOSQUE

Member for

7 years 2 months

10

designs

1

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

wrap_NCV6356_MOSFET

Bob Davis
Designer40261

Bob Davis

Member for

8 years 7 months

76

designs

1

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

wrap_NCV6356_fastsim

Bob Davis
Designer40261

Bob Davis

Member for

8 years 7 months

76

designs

1

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

NCV6356_Demo_Board_fastsim

Bob Davis
Designer40261

Bob Davis

Member for

8 years 7 months

76

designs

1

groups

Add a bio to your profile to share information about yourself with other SystemVision users.

Description

Hierarchical NCV6356 Demo Board buck converter.Ideal switches replace MOSFETs to maximize simulation speed. Best usage is to verify desired behavior over millisecond to tens of ms. Best used to monitor behaviors covering hundreds or more switching cycles.-------------------------------------------------------------------------------------Some useful waveforms can be displayed by probing the chip module. * Expand Fsw_cal and select tbase_rd_out to display Fsw regulation. tbase_rd_out seeks and maintains a constant level of 80 units by setting a controlling value in the Kton waveform. * Select state_of_chip to trace power-up sequence and ishort * Expand Ipk_detect and select N_violations to monitor progress towards ishort detection. * Overlay plots of FBint and Vintl to display voltage resolution,-------------------------------------------------------------------------------------See NCV6356_Demo_Board for an identical design using MOSFET switches to accurately account for power dissipation.-------------------------------------------------------------------------------------See wrap_NCV6356_combined for a schematic representation of the chip model. MOSFET and ideal switch versions are derived from a common netlist generated from this design with portions commented out.Version6_NCV6356_and_DemoBoard combines the above chip model with external buck converter circuitry to produce a single level flattened hierarchy usable to develop and test the chip model.

About text formats

wrap_NCV6356_fastsim

Norm
Designer43361

Norm

Member for

8 years 7 months

328

designs

2

groups

wrap_NCV6356_MOSFET

Norm
Designer43361

Norm

Member for

8 years 7 months

328

designs

2

groups

NCV6356_Demo_Board_fastsim

Norm
Designer43361

Norm

Member for

8 years 7 months

328

designs

2

groups

Description

Hierarchical NCV6356 Demo Board buck converter.Ideal switches replace MOSFETs to maximize simulation speed. Best usage is to verify desired behavior over millisecond to tens of ms. Best used to monitor behaviors covering hundreds or more switching cycles.-------------------------------------------------------------------------------------Some useful waveforms can be displayed by probing the chip module. * Expand Fsw_cal and select tbase_rd_out to display Fsw regulation. tbase_rd_out seeks and maintains a constant level of 80 units by setting a controlling value in the Kton waveform. * Select state_of_chip to trace power-up sequence and ishort * Expand Ipk_detect and select N_violations to monitor progress towards ishort detection. * Overlay plots of FBint and Vintl to display voltage resolution,-------------------------------------------------------------------------------------See NCV6356_Demo_Board for an identical design using MOSFET switches to accurately account for power dissipation.-------------------------------------------------------------------------------------See wrap_NCV6356_combined for a schematic representation of the chip model. MOSFET and ideal switch versions are derived from a common netlist generated from this design with portions commented out.Version6_NCV6356_and_DemoBoard combines the above chip model with external buck converter circuitry to produce a single level flattened hierarchy usable to develop and test the chip model.

About text formats